Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960 by Digital Equipment Corporation (reading like a writer .TXT) π
Indexable Memory Instructions
Arithmetic Instructions
Add (10 usec.) add x Y Operation Code 40
The new C(AC) are the sum of C(Z) and the original C(AC). The C(Z) are unchanged. The addition is performed with 1's complement arithmetic.
If the sum exceeds the capacity of the Accumulator Register, the overflow flip-flop will be set (see Skip Group instructions).
Subtract (10 usec.) sub x Y Operation Code 4
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Shift is an arithmetic operation and is in effect multiplication of the number in the register by 2+N, where N is the number of shifts. Shift or rotate instructions involving more than 33 steps can be used for simulating time delays. 36 rotate steps of the Accumulator will return all information to its original position.
Rotate Accumulator Right(13 usec. maximum for 36 shifts)
rar N Operation Code 671
This instruction will rotate the bits of the Accumulator right N positions, where N is octal digits 7-11 of the instructions word.
Rotate Accumulator Left(13 usec. maximum for 36 shifts)
ral N Operation Code 661
This instruction will rotate the bits of the Accumulator left N Positions, where N is octal digits 7-11 of the instruction word.
Shift Accumulator Right(13 usec. maximum for 36 shifts)
sar N Operation Code 675
This instruction will shift the contents of the Accumulator right N positions, where N is octal digits 7-11 of the instruction word.
Shift Accumulator Left(13 usec. maximum for 36 shifts)
sal N Operation Code 665
This instruction will shift the contents of the Accumulator left N positions, where N is octal digits 7-11 of the instruction word.
Rotate In-Out Register Right(13 usec. maximum for 36 shifts)
rir N Operation Code 672
This instruction will rotate the bits of the In-Out Register right N positions, where N is octal digits 7-11 of the instruction word.
Rotate In-Out Register Left(13 usec. maximum for 36 shifts)
ril N Operation Code 662
This instruction will rotate the bits of the In-Out Register left N positions, where N is octal digits 7-11 of the instruction word.
Shift In-Out Register Right(13 usec. maximum for 36 shifts)
sir N Operation Code 676
This instruction will shift the contents of the In-Out Register right N positions, where N is octal digits 7-11 of the instruction word.
Shift In-Out Register Left(13 usec. maximum for 36 shifts)
sil N Operation Code 666
This instruction will shift the contents of the In-Out Register left N positions, where N is octal digits 7-11 of the instruction word.
Rotate AC and IO Right(13 usec. maximum for 36 shifts)
rcr N Operation Code 673
This instruction will rotate the bits of the combined register right in a single ring N positions, where N is octal digits 7-11 of the instruction word.
Rotate AC and IO Left(13 usec. maximum for 36 shifts)
rcl N Operation Code 663
This instruction will rotate the bits of the combined register left in a single ring N position, where N is octal digits 7-11 of the instruction word.
Shift AC and IO Right(13 usec. maximum for 36 shifts)
scr N Operation Code 677
This instruction will shift the contents of the combined register right N positions, where N is octal digits 7-11 of the instruction word.
Shift AC and IO Left(13 usec. maximum for 36 shifts)
scl N Operation Code 667
This instruction will shift the contents of the combined registers left N positions, where N is octal digits 7-11 of the instruction word.
Skip Group(5 usec.)
skp Y Operation Code 64
This group of instructions senses the state of various flip-flops and switches in the machine. It does not require any reference to memory. The address portion of the instruction selects the particular function to be sensed. All members of this group have the same operation code.
Skip on ZERO Accumulator(5 usec.)
sza Address 100
If the Accumulator is equal to plus ZERO (all bits are ZERO) the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on Plus Accumulator(5 usec.)
spa Address 200
If the sign bit of the Accumulator is ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on Minus Accumulator(5 usec.)
sma Address 400
If the sign bit of the Accumulator is ONE, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on ZERO Overflow(5 usec.)
szo Address 1000
If the overflow flip-flop is a ZERO the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. The overflow flip-flop is cleared by this instruction. This flip-flop is set by addition, subtraction, or division that exceeds the capacity of the Accumulator. The overflow flip-flop is not cleared by arithmetic operations which do not cause an overflow. Thus, a whole series of arithmetic operations may be checked for correctness by a single szo. The overflow flip-flop is cleared by the "Start" Switch.
Skip on Plus In-Out Register(5 usec.)
spi Address 2000
If the sign digit of the In-Out Register is ZERO the Program Counter is indexed one extra position and the next instruction in the sequence is skipped.
Skip on ZERO Switch(5 usec.)
szs Addresses 10, 20, ... 70
If the selected Sense Switch is ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 10 senses the position of Sense Switch 1, Address 20 Switch 2, etc. Address 70 senses all the switches. If 70 is selected all 6 switches must be ZERO to cause the skip to occur.
Skip on ZERO Program Flag(5 usec.)
szf Addresses 0 to 7 inclusive
If the selected program flag is a ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 0 is no selection. Address 1 selects program flag one, etc. Address 7 selects all programs flags. All flags must be ZERO to cause the skip.
The instructions in the One Cycle Skip group may be combined to form the inclusive OR of the separate skips. Thus, if address 3000 is selected, the skip would occur if the overflow flip-flop equals ZERO or if the In-Out Register is positive. The combined instruction would still take 5 microseconds.
Operate Group(5 usec.)
opr Y Operation Code 76
This instruction group performs miscellaneous operations on various Central Processor Registers. The address portion of the instruction specifies the action to be performed.
Clear In-Out Register(5 usec.)
cli Address equal 4000
This instruction clears the In-Out Register.
Load Accumulator from Test Word(5 usec.)
lat Address 2000
This instruction forms the inclusive OR of the C(AC) and the contents of the Test Word. This instruction is usually combined with address 200 (clear Accumulator), so that C(AC) will equal the contents of the Test Word Switches.
Complement Accumulator(5 usec.)
cma Address 1000
This instruction complements (makes negative) the contents of the Accumulator.
Halt
hlt Address 400
This instruction stops the computer.
Clear Accumulator(5 usec.)
cla Address 200
This instruction clears (sets equal to plus 0) the contents of the Accumulator.
Clear Selected Program Flag(5 usec.)
clf Address 01 to 07 inclusive
The selected program flag will be cleared. Address 00 selects no program flag, 01 clears program flag 1, 02 clears program flag 2, etc. Address 07 clears all program flags.
Set Selected Program Flag(5 usec.)
stf Address 11 to 17 inclusive
In-Out Transfer Group(5 usec. without in-out wait)
iot x Y Operation Code 72
The variations within this group of instructions perform all the in-out control and information transfer functions. If bit six (normally the Indirect Address bit) is a ONE, the computer will halt and wait for the completion pulse from the device activated. When this device delivers its completion, the computer will resume operation of the instruction sequence.
An incidental fact which may be of importance in certain scientific or real time control applications is that the time origin of operations following an in-out completion pulse is identical with the time of that pulse.
Most in-out operations require a known minimum time before completion. This time may be utilized for programming. The appropriate In-Out Transfer is given with no in-out wait (bit six a ZERO). The instruction sequence then continues. This sequence must include an iot instruction which performs nothing but the in-out wait. This last instruction must occur before the safe minimum time. A table of minimum times for all in-out devices is delivered with the computer. It lists minimum time before completion pulse and minimum In-Out Register free time.
The details of the In-Out Transfer variations are listed under Input-Output.
The mnemonic codes and addresses for the standard equipment are:
Read Paper Tape Alphanumeric Mode
rpa Address 1
Read Paper Tape Binary Mode
rpb Address 2
Typewriter Output
tyo Address 3
Typewriter Input
tyi Address 4
Punch Paper Tape Alphanumeric Mode
ppa Address 5
Punch Paper Tape Binary Mode
ppb Address 6
The Console of PDP-3 has controls and indicators for the use of the operator. Fig. 4 is a close-up of the control panel of PDP-1, the 18 bit version of PDP-3. All computer flip-flops have indicator lights on the Console. These indicators are primarily for use when the machine has stopped or when the machine is being operated one step at a time. While the machine is running, the brightness of an indicator bears some relationship to the relative duty factor of that particular flip-flop.
Three registers of toggle switches are available on the Console. These are the Test Address (15 bits), the Test Word (36 bits), and the Sense Switches (6 bits). The first two are used in conjunction with the operating push buttons. The Sense Switches are present for manual intervention. The use of these switches is determined by the program (see System Block Diagram and Skip Group Instructions).
Operating Push ButtonsStart β When this switch is operated, the computer will start. The first instruction comes from the memory location indicated in the Test Address Switches.
Stop β The computer will come to a halt at the completion of the current memory cycle.
Continue β The computer will resume operation starting at the state indicated by the lights.
Examine β The contents of the memory register indicated in the Test Address will be displayed in the Accumulator and the Memory Buffer lights.
Deposit β The word selected by the Test Word Switches will be put in the memory location indicated by the Test Address Switches.
Read-In β When this switch is operated, the photoelectric paper tape reader will start operating in the Read-In mode. (see Input-Output).
In addition to the operating push buttons, there are several separate toggle switches.
Single Cycle Switch β When the Single Cycle Switch is on, the computer will halt at the completion of each memory cycle. This switch is particularly useful in debugging programs. Repeated operation of the Continue Switch button will step the program one cycle at a time. The programmer is thus able to examine the machine states at each step.
Test Switch β When the Test Switch is on, the computer will perform the instruction indicated in the Test Address location. It will repeat this instruction either at the normal speed rate or at a single cycle rate if the Single Cycle Switch is up. This switch is primarily useful for maintenance purposes.
Sense Switches β There are six switches on the Console which are present for manual intervention.
STORAGEThe internal Memory System for PDP-3 consists of modules of 4096 words of coincident current magnetic core storage. Each word has 36 bits. The memory modules operate with a read-rewrite cycle time of 5 microseconds. The driving currents of the memory are automatically adjusted to compensate for normal room temperature variations.
Each core memory module consists of the memory stack, the required X and Y switches, the X and Y current sources and sense amplifiers for that stack.
The Memory Address Register, the Memory Buffer Register, and the Memory Timing Controls are considered to be part of the Central Processor. The standard PDP-3 Memory Address Register configuration is built to allow up to 8 modules of core memory (32,768 words).
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