Make: Electronics by Charles Platt (read me a book .TXT) 📕

gates, two 4-input gates, one 8-input gate, or six single-input inverters, as shown in the following table.

2 input

3 input

4 input

8 input

AND

7408

7411

7421

NAND

7400

7410

7420

7430

OR

7432

744078*

NOR

7402

7427

744078*

XOR

7486

XNOR

747266

Inverter

(1 input) 7404

*The 744078 has an OR output and a NOR output on the same chip.

Figures 4-66 through 4-74 show the internal connections of the logic chips that you are most likely to use. Note that the 7402 NOR gate has its logical inputs and outputs arranged differently from all the other chips.

Figure 4-66. Figures 4-66 through 4-74 show pinouts for some of the most widely used logic chips. Note that the inputs of the 7402 are reversed compared with the other chips.

Figure 4-67.

Figure 4-68.

Figure 4-69.

Figure 4-70.

Figure 4-71.

Figure 4-72.

Figure 4-73.

Figure 4-74.

Fundamentals

Rules for connecting logic gates

Permitted:

You can connect the input of a gate directly to your regulated power supply, either positive side or negative side.

You can connect the output from one gate directly to the input of another gate.

The output from one gate can power the inputs of many other gates (this is known as “fanout”). The exact ratio depends on the chip, but you can always power at least ten inputs with one logic output. The output from a logic chip can drive the trigger (pin 2) of a 555 timer. The output from the timer can then deliver 100mA, easily enough for half-a-dozen LEDs or a small relay.

Low input doesn’t have to be zero. A 74HCxx logic gate will recognize any voltage up to 1 volt as “low.”

High input doesn’t have to be 5 volts. A 74HCxx logic gate will recognize any voltage above 3.5 volts as “high.”

See Figures 4-75 and 4-76 for a comparison of permitted voltages on the input and output side of 74HCxx and 74LSxx chips.

Figure 4-75. Each family of logic chips, and each generation in each family, has different standards for input and output minimum and maximum voltages. This diagram shows the standards used by the HC generation of the CMOS family, which was chosen for most of the projects in this book. Note that the current required for input is minimal compared with the current available for output. The power supply to the chip makes up the difference.

Figure 4-76. Because the LS generation of the TTL family has such different tolerances for input voltages and different standards for output voltages, the LS generation of TTL chips should not be mixed in the same circuit as the HC generation of CMOS chips, unless pull-up resistors are used to bring the LS chips into conformance with standards expected by the HC chips. See Experiment 21 for a case study in using LS chips.

Fundamentals

Rules for connecting logic gates (continued)

Not permitted:

No floating-input pins! On CMOS chips such as the HC family, you must always connect all input pins with a known voltage, even if they supply a gate on the chip that you’re not using. When you use a SPST switch to control an input, remember that in its “off” position, it leaves the input unconnected. Use a pull-up or pull-down resistor to prevent this situation. See Figure 4-77.

Figure 4-77. Because a CMOS chip is so sensitive to input fluctuations, a logical input should never be left “floating,” or unattached to a defined voltage source. This means that any single-throw switch or pushbutton should be used with a pull-up or pull-down resistor, so that when the contacts are open, the input is still defined.

Don’t use an unregulated power supply, or more than 5 volts, to power 74HCxx or 74LSxx logic gates.

Be careful when using the output from a logic gate to power even a low-current LED. Check how many milliamps are being drawn. Also be careful when “sharing” the output from a logic gate with the input of another gate, at the same time that it is driving an LED. The LED may pull down the output voltage, to a point where the other gate won’t recognize it. Always check currents and voltages when modifying a circuit or designing a new one.

Never apply a significant voltage or current to the output pin of a logic gate. In other words, don’t force an input into an output.

Never link the outputs from two or more logic gates. If they must share a common output wire, use diodes to protect them from each other. See Figure 4-78.

Figure 4-78. The output from one logic gate must not be allowed to feed back into the output from another logic gate. Diodes can be used to isolate them, or they can be linked via another gate.

In the 74HCxx logic family, each input of a logic gate consumes just a microamp, while the output can source 4 milliamps. This seems paradoxical: how can the chip give out more than it takes in? The answer is that it also consumes power from the power supply attached to pins 7 and 14. That’s where the additional electricity comes from.

Because the logical output from a chip can be greater than the logical input, we can put the chip in a state where it keeps itself “switched on” in a way which is similar to the way the relay in the alarm project was wired to lock itself on. The simplest way to do this in a logic chip is by feeding some of the output back to one of the inputs.

Figure 4-79 shows an AND gate with one of its inputs wired to positive and its other input held low by a pull-down resistor, with a pushbutton that can make the input high. A signal diode connects the output of the chip back to the pushbutton-controlled input. Remember that the diode has a mark on it indicating the end which should be connected to the negative side of the power supply, which in this case will be the end of the 10K resistor.

Figure 4-79. Using a diode, the logical output from a gate can be allowed to feed back